The present invention relates to methods to improve the density of high performance integrated circuit (IC), and more particularly to methods to improve circuit density by stacking active devices vertically using sub-micron thin-film diodes.
A three-dimensional (3D) circuit described in the present invention is a circuit that can have more than one active device on the same substrate area. All integrated circuits of current art cannot have more than one active device in the same area. The most common active devices used by conventional IC are metal-oxide-silicon (MOS) transistors and bipolar transistors. The performance-sensitive regions of those devices are built on single crystal semiconductor substrates to achieve excellent quality control; millions of transistors can be manufactured while their properties are nearly identical. Because no more than one transistor can share the same substrate at the same time, it is impossible to build 3D circuits using such transistors. There were research efforts trying to build 3D circuits by growing multiple layers of single crystal thin films to build 3D circuits. However, building MOS transistors on such thin films with consistency is proven to be extremely difficult. To the best of our knowledge, none of those research efforts were successful.
The dominating active devices used for IC design are transistors. Diodes are seldom used by circuit designers for the difficulty to build a large number of diodes with consistency. Several inventions have been proposed to use Silicon diodes to manufacture read-only memory (ROM). For example, in U.S. Pat. No. 4,399,450 Lohstroh used silicon diodes to manufacture ROM. In U.S. Pat. No. 4,661,927, Graebel used Schottky diodes to manufacture programmable logic array (PLA) and ROM. In U.S. Pat. No. 5,550,075 Hsu et al. proposed a manufacture process to fabricate ROM using smaller diodes on silicon substrate. Vu describes diode-FET logic circuitry in U.S. Pat. No. 4,845,679, while Ogura et al. describes another PLA design in U.S. Pat. No. 4,659,947. The above inventions use diodes built on single crystal substrates. A single-crystal diode is not necessarily smaller than a MOS transistor. Conventional circuits using MOS transistors are better in performance, yield, and cost efficiency. There is no advantage to design IC using single crystal diodes. Such diodes are also not useful in building 3D circuits because they also use single crystal substrates.
Another approach is to use thin-film diodes manufactured by polysilicon or amorphous silicon thin-films. In U.S. Pat. No. 5,272,370 French described thin-film devices for ROM. Sung et al. described silicon diodes manufactured in the plugs of contacts. Such thin-film diodes occupy smaller area, but their quality is very difficult to control. Amorphous or polysilicon semiconductors are materials full of defects. Devices built on such defective materials are very far from ideal. Typically they have much larger reverse bias current than diodes built on single crystal substrates. Existing researches on polysilicon or amorphous silicon are done on large area devices. Large area thin-film diodes can behave with consistency because the effects of defects are averaged in a large area. For high-density IC using sub-micron active devices, it is extremely difficult to manufacture large number of sub-micron thin-film diodes with consistent properties. Since the defect density in each sub-micron diode is nearly unpredictable, the property of individual diode is therefore unpredictable. The diodes described by Sung et al. are extreme cases because those diodes are built within a plug contact hole. The grain sizes of the polysilicon in those sub-micron contact holes must be at deep sub-micron range. It is extremely difficult to have quality control on such devices. All the above inventions require special processing steps to fabricate the diodes. Those additional processing steps increase the total costs of the final products. The materials used to build those diodes require high temperature heat treatments. It is well known to the art that high temperature heat treatments cause problems to other devices on the IC. Due to these and many other problems, to the best of our knowledge, no high density IC has been manufactured successfully using the above prior art inventions.
The primary objective of this invention is, therefore, to provide practical methods to manufacture sub-micron 3D integrated circuits. Another objective is to provide improved thin-film diodes that can be manufactured with consistency. Another objective is to provide design methods to improve the tolerance to the non-ideal properties of thin film diodes. Another primary objective is to achieve the above objectives using fabrication procedures compatible with current art IC technologies.
These and other objectives are accomplished by design and manufacture methods according to the present invention. For simplicity the following descriptions refer the xe2x80x9cpolycrystalline or amorphousxe2x80x9d thin films as xe2x80x9cpolyxe2x80x9d. To use poly diodes as active devices for high density IC, there are two major difficulties. The first difficulty is to build sub-micron thin-film diodes with consistency. The second difficulty is to build them without degrading other IC components. Thin-film diodes are manufactured on materials full of defects. It is extremely difficult to manufacture a large number of sub-micron thin-film diodes with consistent properties when the properties of such small devices are dominated by local defects. Therefore, fabrication procedures of the present invention are developed to make thin-film diodes less sensitive to local defects by moving its active region away from high defect density regions. In the mean time, we also describe design methods to improve tolerance in non-ideal diode properties. The numbers of diodes connected to each node are reduces. Tri-stated drivers are used to reduce the effect of reverse bias leakage. Combinations of fabrication and design improvements make it practical to build IC devices from poly thin film diodes. However, there is another barrier for practical implementation. Poly thin films require high temperature annealing as part of its fabrication procedure. Such high temperature procedures can affect important properties of other IC components, such as the punch-through voltages (Vpt) of sub-micron transistors or the electro-migration (EM) properties of metal lines. Introducing high temperature treatments to an IC fabrication technology requires detailed calibration and development efforts. The tremendous initial cost for the development effort is a major barrier for its implementation. Therefore, this invention discloses manufacture procedures fully compatible with current art IC technologies that does not use additional high temperature procedures and there is no need to use additional masks. This invention demonstrates that current art IC technologies are ready to manufacture the 3D IC devices. Integrated circuits with unprecedented densities can be realized by stacking thin film diodes with common MOS transistors. Device density of logic circuit is improved by nearly one order of magnitude.
While the novel features of the invention are set forth with particularly in the appended claims, the invention, both as to organization and content, will be better understood and appreciated, along with other objects and features thereof, from the following detailed description taken in conjunction with the drawings.